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hopefuly i will be able to get back to regular posting some time in the near future

regards,

eggie

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i will get back to posting soon

Those systems will be powered by anywhere from two to eight cores on a single processor, compared to Intel’s current quad-core solution of strapping two dual-cores chips together. Each individual core will be able to run two simultaneous threads and sitting atop the per-core Level 2 cache will be a shared slab of Level 3 cache accessible to all cores.

Sneak peek: Intel chief Paul Otellini shows an early Nehalem waferSneak peek: Intel chief Paul Otellini shows an early Nehalem wafer(Nehalem derives its codename from the river of the same name in Orgeon, close to Intel’s centre where the architecture and companion next-gen processors were designed. It’ll get a real name closer to launch, and we’re tipping it to be christened as ‘Core 3′. While the current microarchitecure is officially just called Core,the processors built on that foundation are now known as Core 2. Nehalem provides Intel with what must be a welcome chance to clean up the resulting brand confusion)

“First the tick, now the tock” said Stephen Smith, Intel VP and director of the Digital Enterprise Group, referring to Intel’s strategy of delivering processors and microarchitecture in alternate steps across a two year cycle.

“For the beginning of each silicon generation we have a processor that’s derived from the prior generation, and that’s the tick. Then we have a product that’s the larger step, what we call the tock, which is a new microarchitecture to really bring on a leadership level of performance.”

Last year’s 45nm Penryn processor was the tick, and now Intel is gearing up for the tock as Nehalem, which Smith describes as “our ground-up new design optimised for 45nm technology”.

Buy one, get one free: Intel's Stephen Smith says we won't see a single-core Nehalem chip. Even the entry level processor will be dual-coreBuy one, get one free: Intel’s Stephen Smith says we won’t see a single-core Nehalem chip. Even the entry level processor will be dual-core
Beyond its mandatory newer-faster-better bits of technology, Nehalem is “a scalable design”, explains Smith. “It uses a number of building blocks that allows us to build different product configurations, so we can compose various products out of these blocks. Four core is the first to go into production, we also expect to build a monolithic eight core design in 2009 with additional bandwidth.”

Just don’t go looking for a single core Nehalem chip: that’s now ancient history, says Smith. “The lowest implementation we have in mind is a two core design”.

Modular microarchitecture: Nehalem's design treats key system components as building blocks which Intel can assemble in almost any configurationModular microarchitecture: Nehalem’s design treats key system components as building blocks which Intel can assemble in almost any configuration
Among those building blocks are two new pieces of processor plumbing: an integrated memory controller and a dedicated CPU pipeline called QuickPath Interconnect. Well, they’re new for Intel, although AMD already employs both features (for QuickPath Interconnect, read ‘HyperTransport’) as well as Level 3 cache. In those areas, Nehalem is very much Intel’s catch-up ploy.

Nehalem’s memory controller will sit on the individual processor die rather than an external ‘northbridge’ hub and support only DDR3 (DDR2 chips need not apply) with three memory channels per socket to further boost memory bandwidth and reduce latency.

All cached up: Each core in a Nehalem-class processor gets 265KB of L2 cache while sharing anywhere from 4MB to 24MB of L3 cacheAll cached up: Each core in a Nehalem-class processor gets 265KB of L2 cache while sharing anywhere from 4MB to 24MB of L3 cache
This in turn allows Intel to re-engineer Nehalem’s caching. Level 2 cache has been promoted from being per-processor to per-core, but the efficiency of the integrated controller allows this L2 cache to be substantially downsized to just 256Kb for each core. A fat Level 3 cache starting at 4MB is shared by all cores in the processor.

A key difference in the approaches of AMD and Intel is that Intel’s Level 3 ‘inclusive cache hierarchy’ dictates that any data sitting in the per-core L1 or L2 caches must also be present in the shared L3 cache. “If one core needs a piece of data it only has to go as far as checking Level 3, because all the data from all cores is sitting in Level 3″ explains Ronak Singhal, one of Nehalem’s lead engineers. “There’s no latency in fetching data direct from the other core caches”.

The size of the L3 cache “will depend on the number of cores in the product” says Singhal. It’s expected that the dual-core Nehalem processors will start with 4MB of L3 cache, quad-cores will get 8MB and the eight-core servers could get as much as 24MB to play with.

Under the covers: this Nehalem processor shows four 45nm cores, L3 cache, integrated memory controller and the QuickPath Interconnect pipeline all baked onto a single dieUnder the covers: this Nehalem processor shows four 45nm cores, L3 cache, integrated memory controller and the QuickPath Interconnect pipeline all baked onto a single dieThe other key piece of plumbing for multi-processor systems is QuickPath Interconnect, which provides a dedicated pathway between CPU sockets in order to boost dataflow between processors, as well as running between the CPU and the IO hub.

The modular design of Nehalem considers QPI as just another building blocks, allowing Intel to configure high-end systems with multiple QPI pathways.

So when can we expect all this geeky goodness? Intel signed off on Nehalem’s design last year and the first silicon hits production in fourth quarter of the year. The only product at launch will be a six-core server powerplant.

Things hot up in 2009, with the arrival of the quad-core ‘Bloomfield’ desktop chip within the first three months, followed in Q2 by mainstream dual-core desktop (Havendale) and mobile (Auburbdale) processor plus a quad-core extreme mobile chip (Clarksfield).

Nehalem will also be the foundation underpinning Intel’s sixth-generation Centrino platform, codenamed Calpella and due to launch in early 2009, perhaps simultaneously with the mobile processors. (The fifth-gen Montevina platform, now christened Centrino 2 and due around the middle of this year, will use 45nm Penryn-class processors but is built on the Core architecture.)

Price has been a key feature of Atom, previously code-named Silverthorne, since the very first time Intel talked about this product. Intel itself stated that the production cost of the tiny chip may be close to that of a 286 CPU, allowing the company to sell the processor for a low price to open a new market of Mobile Internet Devices (MIDs) and Nettop computers with prices well below the $200 range.

We don’t know the exact price of the Atom CPU yet and will have to wait until the official launch, which appears to be imminent, given the number of systems already being announced to include this processor. Rumors on the Internet currently put the cheapest Atom CPU in a price range between $29 and $49. We expect several SKUs, with the lower end targeting Silverthorne models and the MID/UMPC segment, while Diamondville (possibly dual-core) chips are rumored to go into cheap notebooks and desktops with prices of $500 and less.

Based on Intel’s marketing pitch, the burning question we have been working on for a while, of course, just how profitable this processor will be. We have talked to several sources and received feedback with initial estimates of $2 per CPU and studied reports that the chip may cost about $4. Today, we finally ended up with a source close to the matter and one we consider to be very credible. Industry sources put Atom into the range of “$6-$8″, which would be the production/packaging/shipping cost for the CPU, excluding the Poulsbo chipset. Let’s just assume that Intel will be able to squeeze $40 out of system vendors for Silverthorne and Diamondville - and you have one heck of a profit margin.

Our source was “skeptical” that Silverthorne will in fact be as successful as Intel claims the CPU will be, but noted that “it will be a good cash cow”. Intel is able to put 2500 Atom CPUs on one 300 mm wafer, which would put its production value at about $15,000 to $20,000. Intel should be able to easily hit a 90% yield, which would put the retail value of the CPUs on one wafer at about $100,000 or more. We’re currently digging for more details on the Diamondville and Poulsbo parts, to get a better idea of final bill of materials.

But if Silverthorne takes off in a spectacular manner and sparks a new generation of MIDs and UMPCs, the Atom lineup could end up earning more money than Core 2 does. And that really gives us some food for thought.

Source 

The three-core Phenom X3s, first announced back in September 2007 just ahead of AMD arch-rival Intel’s bi-annual Developer Forum, are detailed just before the next IDF is due to kick off in Shanghai.

The initial line comprises the 2.1GHz 8400 and the 2.3GHz 8600, but AMD’s launch presentation also detailed their successors: the 2.1GHz 8450, the 2.3GHz 8650 and the 2.4GHz 8750.

AMD said the 8450 and 8650 will be priced at, respectively, $160 and $180 when sold in batches of 1000 CPUs - pretty much what the 8400 and 8600 chips cost. The processors have 1.5MB of L2, 512KB per core, and 2MB of shared L3 cache.

Interestingly, AMD’s benchmarks show the 8650 forecast to outperform the current, 2.3GHz X4 9600 by a couple of percentage points and the 2.3GHz 8600 by just over nine per cent. The 2.3GHz 9650 is eight per cent faster than the 9600.

That’s the the improved ‘B3′ core stepping, a feature of the 9×50 and 8×50 CPUs, coming into play. The B3 X3s are expected in May, so there’s arguably little point jumping straight to the 8400 and the 8600. AMD insisted the older core was “perfectly fine”.

AMD also took the wraps off the 2.2GHz 9550, the 2.3GHz 9650, the 2.4GHz 9750 and the 2.5GHz 9850. Like the X3s, these X4s consume up to 95W of power and almost all of them sit on a 3.6GHz HyperTransport bus. The exception is the 9850, which has a bus clocked at 4GHz. It’s also a ‘Black Edition’ part, aimed at gamers and unlocked for overclocking.

AMD announced the 9100e, a 1.8GHz four-core part that consumes 65W. Like the other new X4s, it has 2MB of L2 - again, 512KB per core - and 2MB of shared L3 cache. It runs on a 3.6GHz HT bus.

The part’s pitched at media centre systems, and AMD claimed it was the “only 65W TDP quad-core processor on the market”

The 9550 will cost $199, the 9750 $240 and the 9850 $260, AMD said.

The chip maker also mentioned the existing 3GHz dual-core Athlon X2 6000+, which was handy because the old processor manages to out-perform the 8650 and 8450 in certain AMD-run benchmarks, including MPEG 2 to MPEG 4 video transcoding, and generating a slideshow movie from a stack of JPEG photos.

Actually, AMD’s presentation slide covering the latter test doesn’t mention the three-core part at all - presumably because the comparison with the 6000+ is not flattering. The video test has the 6000+ down as three per cent faster than the 8650.

To be fair, the 8650 is 27 per cent faster than the 6000+ at converting an “HD video file” to a mobile screen-sized MPEG 4 file.

Source

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The geforce 9800GX2 was released, here are some reviews of the new hardware from nVidia

:: MVKTech :: Bjorn3D :: HotHardware :: DriverHeaven :: HardOCP :: TechPowerUp :: Tomshardware :: TweakTown :: Legitreviews ::

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EDIT (14/3/07) : We received new information concerning this board, This board only supports core 2 duo NOT core 2 Quad as originally stated.

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